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Structure of Makefile
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Components of a Makefile
Comments
Rules (Recipe)
Dependency lines
Shell lines
Macros
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Comments start with "#"
You can use "\" to concatenate break-line.
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"make -p" gives a list of all implicit rules and predefined macros
which are applied to the current Makefile
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Final ultimate file (target) should come
at the most-top-location in descending order.
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If multiple files (like main.o this.o) have same dependency,
you can write:
main.o this.o:bitvect.h
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Macros (in other words, variables)
Macro prevents you from typing same strings multiple times.
If you change the value of the macro,
that change affects all texts of the Makefile,
which is efficient.
How to define:
MACRONAME=macro_value
How to use:
${MACRONAME} or $(MACRONAME)
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Example of macro
where macroc creates other macros
# Create HOME macro
HOME=/home/courses/ese101
# Create CPP macro using HOME macro
CPP=${HOME}/cpp
TCPP=${HOME}/tcpp
PROJ=.
INCL=-I${PROJ} -I${CPP} -I${TCPP}
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Predefined macros in Makefile
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$@: full target name
lib.o:aaa.c bbb.c
echo "target $@"
# target lib.o
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$?: list all files which are newer than the current target
In other words, list all files which are created newly than lib.o
lib.o:aaa.c bbb.c
# If file generation time is like 10:10, 10:12, 9:30
echo "newer source file: $?"
# newer source file: aaa.c
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$<: list first dependency file
lib.o:aaa.c bbb.c
echo "first dependency source file: $<"
# first dependency source file: aaa.c
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$*: print name of the target, without suffix (extension)
lib.o:aaa.c bbb.c
echo "target name without suffix: $*"
# target name without suffix: lib
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$^: print names of all dependency files
lib.o:aaa.c bbb.c
echo "names of all dependency files: $&"
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By using those predefined macros,
you can more easily create Makefile.
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